Staff Design Verification Engineer – Lead Sub-System

A global semiconductor leader is seeking a Staff Design Verification Engineer in Assago, Italy. The ideal candidate will have significant experience in digital design and verification, with a strong command of Verilog, System Verilog, and UVM. Responsibilities include verifying complex components using advanced methodologies, mentoring junior engineers, and developing verification plans. This position also involves considerable independence and problem-solving skills, emphasizing a proactive approach in a collaborative environment.
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