Sr. DFT Design Engineer, AWS Machine Learning Acceleration

Overview

Sr. DFT Design Engineer, AWS Machine Learning Acceleration. AWS Utility Computing (UC) provides product innovations and support for Compute, Database, Storage, IoT, Platform, and Productivity Apps services in AWS. Annapurna Labs designs silicon and software that accelerate innovation, delivering cloud solutions with custom chips, accelerators, and software stacks to address challenging problems at scale.

As a member of the Silicon Optimization Engineering Team you’ll be responsible for the design and optimization of hardware in our data centers. You’ll provide leadership in applying new technologies to large-scale server deployments to deliver a world-class customer experience. This is a fast-paced, intellectually challenging role with high standards for performance, quality, and cost, and opportunities to work with thought leaders across multiple technology areas.

Key job responsibilities

• Develop, implement and verify state-of-the-art Design for Test (DFT) architectures
• Work with block designers to integrate DFT implementations
• Work with physical design teams to set up and implement DFT insertion flow
• Develop high coverage and cost-effective DFT methodologies
• Perform RTL coding and verification
• Participate in silicon debugging and write scripts to effectively handle ATE-related data
• Communicate and collaborate with team members across multiple disciplines

About the team

Why AWS: Amazon Web Services is the world’s most comprehensive and broadly adopted cloud platform. We pioneered cloud computing and continue to innovate, earning the trust of customers from startups to Global 500 companies.

Utility Computing (UC): AWS Utility Computing provides foundational and emerging services, supporting customers who require specialized security solutions for their cloud workloads.

Basic Qualifications

• BS degree in EE, CE, or CS
• 5+ years of practical DFT experience with large processor and/or SoC designs
• Knowledge of industry-standard DFT tools and practices (ATPG, JTAG, MBIST) and trade-offs between test quality and test time
• Experience with automation script development

Preferred Qualifications

• MS degree in EE, CE or CS
• Broad knowledge of chip design from micro-architecture to physical design
• Knowledge of design verification (DV) simulation methodologies
• Experience with large gate-level simulation setup and debug with SDF
• Strong programming/scripting skills in Perl, Python, or Tcl
• Experience with standard DFT/SCAN/ATPG tools
• Experience with STA constraints development and analysis for DFT modes
• Practical experience with silicon debugging

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