Sr. ASIC Design Engineer
Descrizione dell'offerta
Sr. ASIC Design Engineer
We’re growing! Our team in Parma (Italy) is seeking a Sr. ASIC Design Engineer.
Responsibilities
- Develop micro‑architecture specifications for a next‑generation Computer Vision processor.
- Design and implement Verilog/SystemVerilog modules for cutting‑edge SOCs, including video compression logic, image processing logic, vector processors, and device/memory controllers.
- Integrate designs, perform logic synthesis, and optimize for timing, area, and power.
- Develop front‑end methodologies and tool flows.
Requirements
- Master’s degree in Electrical Engineering with 0–4 years of experience.
- Strong understanding of VLSI/ASIC design, computer architecture, and logic design.
- Proficient in Verilog/SystemVerilog.
- Programming skills in scripting languages such as Python and Perl.
- Experience with design verification and functional coverage.
- Excellent communication skills and a good team player.
- Knowledge of logic synthesis and timing closure is mandatory.
- Plus: experience in image/video processing, computer vision, or machine learning.
Contact
To apply, please submit resume with subject: JOB#VLSI to or apply online on the Ambarella website.
Equal Opportunity
As an Equal Opportunity/Affirmative Action Employer, Vislab and Ambarella recruit qualified applicants without regard to race, color, national origin, sex, physical disability, or veteran status.
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Job Details
- Seniority level: Associate
- Employment type: Full‑time
- Job function: Research
- Industries: Software Development and Appliances, Electrical, and Electronics Manufacturing