Senior Verification Engineer: Verilog/UVM, Global Team

A leading semiconductor company in Milano is seeking a Junior/Senior Verification Engineer to develop block level verification test plans for integrated circuits using Verilog and UVM. The ideal candidate should have at least 3 years of experience, be familiar with EDA tools, and possess excellent teamwork and problem-solving skills. This role offers flexible full-time or part-time hours in a dynamic work environment focused on innovation and inclusion.
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