Senior Principal Mixed-Signal Verification Engineer (d/ m/ f)

The ams OSRAM Group is a global leader in intelligent sensors and emitters. We combine light with intelligence and passion with innovation, thereby enriching people's lives. Our approximately 20,000 employees worldwide focus on innovations in the fields of sensing, lighting, and visualization to make travel safer, medical diagnostics more precise, and everyday communication more engaging.

Senior Principal Mixed‑Signal Verification Engineer (d/ m/ f)

Premstätten (Styria), Pavia (Lombardy) – ams-OSRAM AG

Responsibilities

• Develops and leads the maintenance of high quality AMS/DMS behavioral models and reusable model libraries (EEnet/UDN), defining modeling standards and ensuring consistency across products
• Runs DMS simulations and correlates them with transistor level Spectre results, performing root cause analysis, refining models, and using analog judgment to distinguish real circuit issues from modeling limitations
• Builds, extends, and maintains DMS verification environments using SystemVerilog and UVM MS, including testbenches, mixed signal assertions, critical scenarios, and coverage. Also designs and maintains the mixed signal regression infrastructure (capacity, debugging, failure analysis)
• Executes verification across PVT variations and interprets corner results effectively
• Automates simulation execution, data analysis, correlation, and reporting using Python to improve efficiency and traceability
• Analyzes schematics, predicts circuit behavior, and solves complex analog or mixed signal problems independently
• Defines AMS/DMS coverage metrics and formal sign off criteria, including coverage closure, transistor level correlation, interface validation, and specification compliance
• Collaborates effectively with Digital Design, SoC Verification, Firmware, and Architecture teams to ensure proper functional integration and interface consistency

Qualifications

• University degree in Electronics or other related technical education
• 10+ years of experience in analog or mixed‑signal circuit design or analog verification with direct involvement in projects through tape‑out or product completion
• Deep analog circuit expertise applied to DMS verification using SystemVerilog EEnet/UDN, accurately modeling real world effects such as loading, impedance interactions, noise and non‑idealities
• Strong expertise in analog circuits (op amps, references, ADC/DAC architectures, low noise front ends, sensor interfaces, bio signal circuits)
• Deep knowledge of analog performance metrics (offset, drift, noise, CMRR, PSRR, THD, SFDR, ENOB, bandwidth, settling time, INL/DNL, stability)
• Strong technical communication skills with the ability to clearly explain complex analog concepts to cross‑functional teams
• Knowledge of English is mandatory, German / Italian is an advantage depending on the office location

Benefits

For Austria: We offer competitive salaries and additional benefits based on your performance, experience and qualification.

The employment is in accordance with the collective salary and wage agreement for employees of the electrical and electronics industry, employment group H. We offer a higher compensation depending on your expertise and skills.