Senior Layout Engineer for DDR/HBM/UCIe IPs

A global semiconductor leader in Milan seeks an experienced engineer for layout design in silicon IP. You will develop layouts for DDR, HBM, and UCIe PHYs, ensuring high-quality physical design while collaborating across teams. Candidates should have over 2 years of experience in layout development and physical verification. Strong understanding of deep submicron effects and expertise in advanced process technologies are essential. This is an exciting role for individuals passionate about innovation and technology.
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