Senior Engineer, Digital Design Engineering

In this role you will drive digital design for FPGA-based prototypes and ASIC readiness, collaborating with cross-functional teams to translate RTL into silicon. You will shape architectures, verify complex blocks, and ensure timing, area, and power targets across the product lifecycle. The position offers exposure to cutting-edge FPGA/ASIC methodologies and interaction with customers and stakeholders, contributing to high-impact silicon solutions for embedded systems. FPGA prototyping and HDL-based design Developing models and self-checking mechanisms for FPGA HW & SW co-design and architectural block specification Verilog/SystemVerilog RTL design with emphasis on AXI/AHB and ARM cores Define timing constraints and perform static timing analysis Coordinate with verification, analog, and implementation teams to bring RTL to silicon Interact with customers and stakeholders to align on functionality and protocols Design to meet targets for timing, area, low-power, manufacturing test and timing IP block design and integration; mixed-signal verification and co-simulation Verify blocks using UVM and support product roadmap alignment Bachelor's in Electronic Engineering or equivalent; Master's may be preferred Architectural design of complex SOCs with processors Deep knowledge of FPGA development flow and FPGA modelling Verilog/SystemVerilog RTL design with emphasis on AXI/AHB and ARM cores Experience with timing, area, low-power, DFT, and manufacturing test constraints Ability to work with verification and analog teams; cross-functional collaboration Strong interpersonal, teamwork, and communication skills; precise documentation Self-motivation, enthusiasm, and quick adoption of new technologies Proven problem-solving skills and ability to work in diverse teams Experience with RTL-to-silicon flow and interaction with implementation teams In this role you will drive digital design for FPGA-based prototypes and ASIC readiness, collaborating with cross-functional teams to transl… #J-18808-Ljbffr