PRINCIPAL PHYSICAL DIGITAL DESIGN ENGINEER
Descrizione dell'offerta
Principal Physical Digital Design Engineer
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The position in brief
Job title: Principal Physical Digital Design Engineer
Workplace: Pavia/Bologna, Italy
Deadline:
How to apply: Apply through LinkedIn
The Foundation “Italian Center for the Design of Semiconductor Integrated Circuits,” also known as the Chips‑IT Foundation, is a non‑profit research and technology organization under the supervision of the Ministries of Industry. The Foundation is Italy’s first RTO (Research and Technology Organization) vertically focused on semiconductor research and stands as a center of excellence in frontier research on semiconductor design, as well as a pivotal center of the Italian semiconductor ecosystem and expertise.
Missions Of The Foundation
- Promote the design and development of integrated circuits.
- Strengthen the system of professional training in the field of microelectronics.
- Ensure the establishment of a network of universities, research centers and enterprises that fosters innovation and technology transfer in the field.
Role
The Chips‑IT Foundation is expanding its microelectronics design team and is seeking a highly experienced Principal Physical Design Engineer to play a key technical leadership role in advanced System‑on‑Chip (SoC) development programs. The position will contribute to cutting‑edge R&D activities, working closely with architecture, RTL, verification, and technology teams in a state‑of‑the‑art microelectronics design environment. The Principal Physical Design Engineer will be responsible for leading and executing complex digital design flows for advanced semiconductor nodes. The role requires deep hands‑on expertise across the full physical implementation lifecycle, from netlist handoff through place & route, signoff, and tape‑out, while also providing technical mentorship and driving best practices within the design team. The work can be carried out either in Pavia or in Bologna.
Key Responsibilities
- Lead and execute end‑to‑end physical design flows for complex SoCs and IP blocks, from RTL handoff to GDSII.
- Collaborate closely with RTL, verification, DFT, and architecture teams to resolve design and implementation issues.
- Work with PDKs and technology teams to ensure correct usage of advanced‑node design rules and constraints.
- Develop, document, and improve physical design methodologies, scripts, and automation flows.
- Mentor junior engineers and provide technical leadership across physical design activities.
Required Qualifications
- Master’s degree (or PhD) in Electrical Engineering, Computer Engineering, or a related field.
- Extensive hands‑on experience in physical design for advanced technology nodes (e.g., 16 nm and below).
- Strong expertise with industry‑standard EDA tools (Cadence, Synopsys, Siemens).
- Solid understanding of semiconductor fabrication processes and foundry design requirements.
- Proficiency in Tcl, Python, or Perl for flow automation and methodology development.
- Experience supporting multiple tape‑outs in advanced nodes.
What We Offer
- Competitive compensation and contract type, to be negotiated based on qualifications and experience.
- Possibility to enter into a PhD conjugating your job with a research program that will grant you the PhD title.
- Lunch tickets.
- Private health care coverage depending on your role and contract.
- Structured growth path, with ongoing access to training and updates.
- Networking opportunities with industry‑leading professionals.
- International environment.
- Hybrid work policy.
- Tax deductions: Candidates from abroad, comprising Italian citizens, who have carried scientific research activity abroad and meet specific requirements, may be entitled to a taxable income deduction up to 90 % for a period of 6 to 13 years.
Non verrà redatta e pubblicata alcuna graduatoria o elenco degli idonei.
La Fondazione Si Riserva La Facoltà Di
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