Principal DFT Engineer

Overview

My client, a leading European semiconductor start-up company, is looking for a Principal Design for Test (DFT) Engineer to join their team.

You'll play a pivotal role in architecting and implementing innovative testability solutions for our multicore in-memory-compute SoC. This is an opportunity to contribute to cutting-edge semiconductor advancements in a collaborative and dynamic environment.

Key responsibilities:

• Develop and implement DFT strategies for multicore in-memory-compute SoCs.
• Collaborate with cross-functional teams to ensure seamless integration of test solutions.
• Drive innovation by advancing testability methodologies and infrastructure.

Qualifications:

• Experience : Senior-level expertise in DFT engineering.
• Skills : Proficiency in SystemVerilog RTL, TCL, Python, and Unix/Linux.
• Core Knowledge : Hierarchical scan, ATPG, Memory BIST, JTAG/IJTAG, fault simulation, silicon debug, and gate-level verification.
• Tools : Familiarity with Siemens (Tessent), Cadence, or Synopsys DFT tools.
• Additional Expertise (a plus): IEEE standards (1149, 1500, 1687), synthesis flow, timing analysis, and Siemens DFT tools.
• Strong problem-solving abilities, effective communication skills, and a passion for innovation in the semiconductor industry.