Lead IC Layout Engineer

At 2D Photonics and CamGraPhIC we develop ultra-high bandwidth, low latency optical interconnects for generative AI, cellular, and high bandwidth data transfer applications.

Our Graphene Integrated Photonics (GIP) ofers superior capabilities for next-generation optical transceivers. The way we incorporate graphene with silicon photonics preserves its unique electrooptical properties and enables a next generation of optical interconnect devices with reduced electronic complexity, improved energy consumption, and higher channel density.

At CamGraPhIC in Pisa, Italy we run the 700 sqm Inphotec Graphene Photonics development facility, where our team of industry-leading scientists, process development and photonics engineers are pioneering the design and fabrication of Photonic Integrated Circuits (PICs) incorporating Graphene.

Who are we looking for?

We are seeking a Lead IC Layout Engineer to establish and lead the layout function for advanced

Electronic Integrated Circuits (EICs). This role is ideal for a hands-on technical leader who can build and

mentor a layout team while personally owning critical analog, digital, and mixed-signal layout at 7 nm and

below. You will work closely with circuit designers to deliver silicon-ready layouts that meet performance,

reliability, and manufacturability requirements.

What will you be doing?

• Build, lead, and mentor a high-performing IC layout team

• Own hands-on layout of critical analog, digital, and mixed-signal blocks in advanced FinFET

CMOS nodes (7 nm and below)

• Defne and maintain layout methodologies, best practices, and quality standards

• Manage the CAD and PDK environment, including tool setup, version control, and foundry

updates

• Work closely with circuit designers to support physical implementation, foorplanning, and

constraint-driven layout

• Perform and sign of full-chip DRC, LVS, and parasitic extraction (PEX)

• Assemble complete EIC layouts ready for tape-out, including top-level integration and

verifcation

• Support power integrity, signal integrity, and reliability requirements (EM/IR, ESD, latch-up)

• Prepare fnal databases and documentation for foundry mask release and tape-out

What we need to see?

• Extensive experience in IC layout for advanced CMOS FinFET technologies (7 nm and below)

• Proven ability to lead and grow an IC layout team while remaining hands-on

• Strong experience with both analog and digital layout, including mixed-signal integration

• Deep understanding of advanced-node design rules, DFM, and variability considerations

• Hands-on expertise with DRC/LVS/PEX fows and full-chip sign-of

• Experience working closely with circuit designers to optimize performance and extract

parasitics

• Familiarity with Cadence Virtuoso and associated verifcation tools

• Track record of successful tape-outs and foundry mask releases

• Strong communication skills and ability to collaborate across design, verifcation, and

manufacturing teams