Lead IC Layout Architect for 7nm & Below

A leading optical technology firm in Bergamo, Italy is seeking a Lead IC Layout Engineer to establish and lead the layout function for advanced Electronic Integrated Circuits. The ideal candidate will have extensive experience in IC layout for CMOS FinFET technologies at 7 nm and below, as well as the ability to lead and mentor a layout team. Responsibilities include hands-on layout of critical blocks, managing the CAD environment, and collaborating closely with circuit designers. This role offers an opportunity to work in a pioneering environment focused on next-generation optical technologies.
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