Junior IC Verification Engineer | Gate‑Level to System Verif

Eggtronic srl. is seeking a junior IC Verification Engineer to join the IC team in Modena, Italy. In this role, you will be responsible for performing gate-level and mixed-signal simulations, as well as block level and system-level verification. Essential qualifications include a basic knowledge of HDL languages (SystemVerilog, Verilog, VHDL), scripting languages like Tcl and Python, and firmware development. The role also offers employee fringe benefits, healthcare check-ups, an annual bonus, and a friendly working environment.
#J-18808-Ljbffr