Junior FPGA Engineer: RTL, VHDL & Hardware Design

RINA · Roma, Lazio, Italia · · 50€ - 70€


Descrizione dell'offerta

A multinational engineering company is seeking a Junior Hardware Designer/FPGA to support FPGA-based solutions development in Rome. Key responsibilities include analyzing FPGA architectures, developing RTL code using VHDL, and assisting with verification of FPGA functionalities. The ideal candidate has a Bachelor's or Master's in Electrical or Electronic Engineering and knowledge of VHDL. The role promises a supportive work environment that values innovation and equal opportunities.
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Candidatura e Ritorno (in fondo)