Evaluation and Design of GaN-Based Gate Driver Architectures for High-Efficiency Inverter Modules

The primary goal of this thesis is to investigate the feasibility and advantages of Gallium Nitride (GaN) technology as a key component in inverter modules compared to existing solutions such as Silicon Carbide (SiC) MOSFETs and Insulated Gate Bipolar Transistors (IGBTs) .

The work will be divided into three main phases.

Phase 1: Technology Analysis and Benchmarking

Objective: Conduct an in-depth study of GaN technology for inverter applications.

Activities:

• Review state‑of‑the‑art literature and technical papers to understand current trends and advancements in GaN‑based power electronics.
• Benchmark GaN against alternative technologies (SiC IGBT) in terms of:
  Switching speed
  Efficiency
  Thermal performance
  Reliability and cost implications
• Analyze what major OEMs and semiconductor companies are currently implementing in this domain.
• Collaborate with NXPs Application and Product Definition Team to gather expert insights and feedback on GaN adoption strategies.

Expected Outcome: A comprehensive report summarizing the advantages, limitations and market positioning of GaN technology for inverter modules.

Phase 2: Gate Driver Architecture Design for GaN

Objective: Develop and validate a gate driver architecture optimized for GaN devices.

Activities:

• Focus on GaNagoza requirements:
  High‑speed switching
  Low parasitic inductance
  Robust protection mechanisms
• Perform analog design activities including:
  Architecture definition and evaluation
  Behavioral modeling and simulation
  PVT (Process Voltage Temperature) analysis
• Address industrialization aspects ensuring the design meets manufacturability and reliability standards.
• Supervise and support layout design activities considering:
  Parasitic effects
  Signal integrity
  Impact of layout on performance

Expected Outcome: A fully simulated and optimized gate driver architecture for GaN ready for prototyping.

Phase 3: Bench Characterization and Validation

Objective: Validate the performance of a previous‑generation GaN gate driverPoz in NXPs laboratory environment.

Activities:

• Perform hands‑on bench testing and waveform analysis.
• Identify critical issues and limitations in the existing design.
• Document findings in a detailed characterization report including:
  Measured performance vs. simulated expectations
  Recommendations for improvement

Expected Outcome: A complete validation report highlighting gaps and providing actionable insights for next‑generation designs.

Key Deliverables

Literature review and benchmarking report on GaN vs. SiC/IGBT technologies.
Gate driver architecture design documentation including simulations and layout considerations.
Bench characterization report of the previous‑generation gate driver.

Required Skills

• Analog circuit design and simulation (SPICE‑based tools)
• Layout design (Cadence Virtuoso or equivalent)
• Power electronics fundamentals
• Laboratory measurement techniques (oscilloscopes, power analyzers)
• Collaboration with cross‑functional teams (Application Engineering, Product Definition)

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