Analog Layout Engineer

About Chipright

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Chipright is a specialist semiconductor recruitment and consulting firm, supporting global IC design companies across Analog, Mixed‑Signal, RF, and Digital domains. We partner with organisations that value first‑time‑right silicon , long‑term technical quality, and experienced engineering talent.

Focused. Trusted. Proven. Right First Time.

The Role:

We are seeking a Senior Analog Layout Engineer with 5+ years of industry experience to join a highly skilled IC design environment working on advanced Analog and Mixed‑Signal silicon.

This is a permanent position , suited to an engineer who can take ownership of layout blocks and top‑level integration, work closely with analog designers, and contribute to delivering robust, production‑ready silicon.

Key Responsibilities

• Full‑custom Analog / Mixed‑Signal IC layout from schematic through to GDSII
• Block‑level and top‑level layout, floor planning, and final chip integration
• Development of matching‑critical and noise‑sensitive structures (e.g. current mirrors, bandgaps, ADCs, regulators, RF blocks)
• Close collaboration with Analog Design, Verification, CAD, and Integration teams
• Sign‑off ownership including:
• DRC / LVS
• ERC / PERC
• Antenna checks
• EM / IR reliability analysis
• Supporting LVS debug, extraction, post‑layout simulation, and tape‑out activities
• Contributing to layout methodology, best practices, and first‑pass silicon success

Required Experience & Skills

• 5 to 1o years hands‑on experience in Analog / Mixed‑Signal / RF IC Layout
• Strong expertise in full‑custom layout for performance‑critical analog circuits
• Proficiency with Cadence Virtuoso layout tools:
• Virtuoso Layout XL / GXL / EXL
• Constraint‑driven layout and matching techniques
• Physical verification experience using:
• Calibre , Assura , PVS / Pegasus
• Strong understanding of deep sub‑micron layout challenges:
• device matching & symmetry
• parasitics (R, C, coupling)
• EM / IR, antenna effects, reliability rules
• Experience working to tape‑out deadlines in multi‑disciplinary xdwybme teams
• Proven experience in delivering high-speed or precision analog circuits, preferably in multiple process nodes
• Be accountable throughout the full development cycle: floorplan, layout, verification, delivery, and support

Technology Experience (Typical)

• CMOS / FinFET / SOI / FDSOI processes
• Foundries such as TSMC, GlobalFoundries, Samsung, X‑Fab (project‑dependent)
• Process nodes ranging from 10nm down to 3nm advanced

What This Role Offers

• Permanent, long‑term role working on real silicon , not short‑term churn
• Exposure to complex analog and mixed‑signal designs
• Global collaboration with experienced design and layout engineers